Some embodiments of the present disclosure relate generally to quadrature clock generation.
Serial links include a transmitter connected to a receiver via a channel. In many cases the transmitter forwards a complimentary high-speed clock to the receiver in addition to any data. The receiver typically performs compensation for the clock and data signals to account for any skew introduced by the channel. Accurate de-skewing often uses a phase-interpolator which in turn, often uses a quadrature clock. A quadrature clock (Q) is a clock that is offset by 90 degrees from an in-phase clock (I).
FIG. 1 depicts a related art receiver configured to generate a quadrature clock using a Delay-Locked Loop (DLL).
Referring to FIG. 1, related art systems have generally relied upon an analog front-end (AFE) 120 to amplify an incoming signal and a DLL 100 to generate the in-phase and quadrature clock components (e.g., I/Q). A signal is supplied by a transmitter via the channel 110 and received at an analog front end 120 of the receiver. The analog front end 120 may, for example, include one or more filtering and amplification stages. The DLL 100 receives the modified signal from the analog front end 120 and generates the in-phase component and quadrature component (I/Q) of the clock. The DLL 100 includes multiple components such as delay circuitry 130, a phase detector 140, and a charge pump 150. These components can take up a large area and consume a relatively high amount of power. Furthermore, the DLL 100 introduces a number of extra stages in the clock path which may increase jitter. Thus, an improved system and method that requires less power, space, and less stages in the clock path is desired.
The above information is only for enhancement of understanding of the background of embodiments of the present disclosure, and therefore may contain information that does not form the prior art.